Field of the Invention
The present invention relates to a processing method for a package wafer whose front surface side is sealed by a resin.
Description of the Related Art
In recent years, the wafer level chip size package (WL-CSP), which is carried out to packaging in the wafer state, has been attracting attention. In the WL-CSP, a redistribution layer and electrodes are provided and are sealed by a resin or the like on the front surface side of devices formed on a wafer, and the wafer after the sealing (WL-CSP substrate) is divided by a method such as laser processing. This WL-CSP is useful for size reduction of the package because the size of the chip obtained by the dividing is directly the size of the package.
By the way, when the laser processing of the wafer is carried out, alignment to adjust the position, orientation, and so forth of the wafer is carried out normally on the basis of a characteristic key pattern in the device. On the other hand, in the above-described WL-CSP substrate, many devices are covered by a resin or the like and the number of exposed key patterns is small. For this reason, in the existing method, there is a problem that an operator needs to select the key pattern to be used and it takes a long time to carry out the alignment.
To address this problem, there have been proposed a method in which solder balls or the like that are exposed on the upper surface of a resin and function as electrodes are used as a target pattern (for example, refer to Japanese Patent Laid-open No. 2013-171990), a method in which the intersection of a planned dividing line exposed at the outer circumferential part of a package wafer and the outer circumferential edge is used as the basis (for example, refer to Japanese Patent Laid-open No. 2013-74021), and so forth. According to these methods, alignment can be carried out in a short time even with a package wafer like a WL-CSP substrate in which the number of exposed key patterns is small.